Specifications
| book-author | M. Morris R. Mano, Michael D. Ciletti |
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| publisher | Pearson; 5th edition |
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| file-type | PDF |
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| pages | 576 pages |
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| language | English |
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| asin | B006Y14OF6 |
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| isbn10 | 132774208 |
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| isbn13 | 9780132774208 |
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Book Description
The classic authoritative textbook on digital design has been given a fresh new look in Mano and Ciletti's Digital Design; 5th edition (PDF), which is available now. The fundamental ideas of digital design are presented in a concise and easily understandable format in this ebook. This ebook contains instructions that are applicable to a wide range of digital applications and outlines the fundamental tools that are necessary for the construction of digital circuits.
P.S. In addition to that, we are selling the test bank for the fifth edition of Digital Design With an Introduction to the Verilog HDL, as well as ISM and other resources. Get in touch for further information.
PLEASE NOTE That the Digital Design 5e PDF eBook is all that is included in this purchase. There are no access codes provided.
Table of contents
Table of contents :
Cover……Page 1
Title Page……Page 5
Copyright Page……Page 6
Contents……Page 7
Preface……Page 11
1.1 Digital Systems……Page 19
1.2 Binary Numbers……Page 21
1.3 Number-Base Conversions……Page 24
1.4 Octal and Hexadecimal Numbers……Page 26
1.5 Complements of Numbers……Page 28
1.6 Signed Binary Numbers……Page 32
1.7 Binary Codes……Page 36
1.8 Binary Storage and Registers……Page 45
1.9 Binary Logic……Page 48
2.2 Basic Definitions……Page 56
2.3 Axiomatic Definition of Boolean Algebra……Page 58
2.4 Basic Theorems and Properties of Boolean Algebra……Page 61
2.5 Boolean Functions……Page 64
2.6 Canonical and Standard Forms……Page 69
2.7 Other Logic Operations……Page 76
2.8 Digital Logic Gates……Page 78
2.9 Integrated Circuits……Page 84
3.2 The Map Method……Page 91
3.3 Four-Variable K-Map……Page 98
3.4 Product-of-Sums Simplification……Page 102
3.5 Don't-Care Conditions……Page 106
3.6 NAND and NOR Implementation……Page 108
3.7 Other Two-Level Implementations……Page 115
3.8 Exclusive-OR Function……Page 121
3.9 Hardware Description Language……Page 126
4.2 Combinational Circuits……Page 143
4.3 Analysis Procedure……Page 144
4.4 Design Procedure……Page 147
4.5 Binary Adder–Subtractor……Page 151
4.6 Decimal Adder……Page 162
4.7 Binary Multiplier……Page 164
4.8 Magnitude Comparator……Page 166
4.9 Decoders……Page 168
4.10 Encoders……Page 173
4.11 Multiplexers……Page 176
4.12 HDL Models of Combinational Circuits……Page 182
5.2 Sequential Circuits……Page 208
5.3 Storage Elements: Latches……Page 211
5.4 Storage Elements: Flip-Flops……Page 214
5.5 Analysis of Clocked Sequential Circuits……Page 222
5.6 Synthesizable HDL Models of Sequential Circuits……Page 235
5.7 State Reduction and Assignment……Page 249
5.8 Design Procedure……Page 254
6.1 Registers……Page 273
6.2 Shift Registers……Page 276
6.3 Ripple Counters……Page 284
6.4 Synchronous Counters……Page 289
6.5 Other Counters……Page 296
6.6 HDL for Registers and Counters……Page 301
7.1 Introduction……Page 317
7.2 Random-Access Memory……Page 318
7.3 Memory Decoding……Page 325
7.4 Error Detection and Correction……Page 330
7.5 Read-Only Memory……Page 333
7.6 Programmable Logic Array……Page 339
7.7 Programmable Array Logic……Page 343
7.8 Sequential Programmable Devices……Page 347
8.2 Register Transfer Level Notation……Page 369
8.3 Register Transfer Level in HDL……Page 372
8.4 Algorithmic State Machines (ASMs)……Page 381
8.5 Design Example (ASMD Chart)……Page 389
8.6 HDL Description of Design Example……Page 399
8.7 Sequential Binary Multiplier……Page 409
8.8 Control Logic……Page 414
8.9 HDL Description of Binary Multiplier……Page 420
8.10 Design with Multiplexers……Page 429
8.11 Race-Free Design (Software Race Conditions)……Page 440
8.12 Latch-Free Design (Why Waste Silicon?)……Page 443
8.13 Other Language Features……Page 444
9.1 Introduction to Experiments……Page 456
9.2 Experiment 1: Binary and Decimal Numbers……Page 461
9.3 Experiment 2: Digital Logic Gates……Page 464
9.4 Experiment 3: Simplification of Boolean Functions……Page 466
9.5 Experiment 4: Combinational Circuits……Page 468
9.6 Experiment 5: Code Converters……Page 470
9.7 Experiment 6: Design with Multiplexers……Page 471
9.8 Experiment 7: Adders and Subtractors……Page 473
9.9 Experiment 8: Flip-Flops……Page 475
9.10 Experiment 9: Sequential Circuits……Page 478
9.11 Experiment 10: Counters……Page 479
9.12 Experiment 11: Shift Registers……Page 481
9.13 Experiment 12: Serial Addition……Page 484
9.14 Experiment 13: Memory Unit……Page 485
9.15 Experiment 14: Lamp Handball……Page 487
9.16 Experiment 15: Clock-Pulse Generator……Page 491
9.17 Experiment 16: Parallel Adder and Accumulator……Page 493
9.18 Experiment 17: Binary Multiplier……Page 496
9.19 Verilog HDL Simulation Experiments and Rapid Prototyping with FPGAs……Page 498
10.1 Rectangular-Shape Symbols……Page 506
10.2 Qualifying Symbols……Page 509
10.3 Dependency Notation……Page 511
10.4 Symbols for Combinational Elements……Page 513
10.5 Symbols for Flip-Flops……Page 515
10.6 Symbols for Registers……Page 517
10.7 Symbols for Counters……Page 520
10.8 Symbol for RAM……Page 522
Appendix……Page 525
Answers to Selected Problems……Page 539
B……Page 557
C……Page 558
E……Page 559
I……Page 560
L……Page 561
Q……Page 562
S……Page 563
V……Page 564
X……Page 565
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