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RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design

Download RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design written by Stuart Sutherland in PDF format. This book is under the category Computers and bearing the isbn/isbn13 number 1546776346/9781546776345. You may reffer the table below for additional details of the book.

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Specifications

book-author

Stuart Sutherland

publisher

Sutherland HDL; Inc.

file-type

PDF

pages

488 pages

language

English

asin

B071GY6MND

isbn10

1546776346

isbn13

9781546776345


Book Description

This ebook is both a reference and a tutorial for engineers who use the SystemVerilog Hardware Description Language (HDL) to design FPGAs and ASICs. RTL Modeling with SystemVerilog for Simulation and Synthesis; (PDF) shows how to write SystemVerilog models at the Register Transfer Level (RTL) that simulate and synthesize appropriately; with a stress on proper coding styles and best practices.

SystemVerilog is the newest generation of the original Verilog language; and includes many important capabilities to competently and more accurately model increasingly complex designs. This ebook reflects the SystemVerilog-2012/2017 standards.

The audience for this ebook is for engineers who already know; or who are studying; digital design engineering. The ebook does not present digital design theory; it demonstrate s how to apply that theory to write RTL models that simulate and synthesize correctly. (Note: This ebook provides a more comprehensive examination of the RTL modeling aspects of SystemVerilog than the author’s older “SystemVerilog for Design” ebook. The older ebook was written for an audience that already knows the Verilog-2001 language and only provides the extensions that SystemVerilog adds to Verilog-2001. This ebook encompasses the full; combined Verilog and SystemVerilog language; with more focus on best coding styles for simulation and synthesis.)

The maker of the original Verilog Language; Phil Moorby says about this ebook (excerpt from the ebook’s Foreward): “Many distributed textbooks on the design side of SystemVerilog assume that the reader is familiar with Verilog; and simply describe the new extensions. It is time to exit from the stepping-stones and to teach a single concise and consistent language in a single ebook; and maybe n much mot even refer to the old ways at all! If you are a designer of digital systems; or a verification engineer looking for bugs in these designs; then SystemVerilog will present you with substantial benefits; and this ebook is a wonderful place to learn the design aspects of SystemVerilog.

NOTE: The product only includes the ebook; RTL Modeling with SystemVerilog for Simulation and Synthesis in PDF. No access codes are included.

 

book-author

Stuart Sutherland

publisher

Sutherland HDL; Inc.

file-type

PDF

pages

488 pages

language

English

asin

B071GY6MND

isbn10

1546776346

isbn13

9781546776345

Table of contents


Table of contents :
Title page
……Page 1
Other books authored or co-authored by Stuart Sutherland
……Page 2
Dedication……Page 5
About the Author……Page 6
Table of Contents……Page 7
List of Examples……Page 15
List of Figures……Page 18
Foreword……Page 21
Why this book……Page 23
Book examples……Page 25
Simulators and synthesis compilers used in this book……Page 26
Acknowledgements……Page 27
1.1 Verilog and SystemVerilog — a brief history……Page 28
1.1.1 The Original Verilog……Page 29
1.1.3 IEEE Verilog-95 and Verilog-2001……Page 30
1.1.4 SystemVerilog extensions to Verilog — a separate standard……Page 31
1.1.5 SystemVerilog replaces Verilog……Page 32
1.2.1 Abstraction……Page 33
1.2.2 Gate-level models……Page 34
1.2.3 RTL models……Page 37
1.2.4 Behavioral and transaction-level models……Page 38
1.4.1 Standard cell ASICs……Page 39
1.4.2 FPGAs……Page 42
1.4.3 RTL coding styles for ASICs and FPGAs……Page 43
1.5 SystemVerilog simulation……Page 44
1.5.2.1 Source code order……Page 48
1.5.2.3 Single-file and multi-file compilation……Page 49
1.5.3 Simulation time and event scheduling……Page 50
1.5.3.1 Time units and time precision……Page 51
1.5.3.2 Propagation delays……Page 52
1.5.3.3 Simulating time and simulation event scheduling……Page 53
1.5.3.5 Active and NBA Update events, blocking and nonblocking assignments……Page 54
1.5.3.6 Event scheduling example……Page 56
1.6 Digital synthesis……Page 58
1.6.1 SystemVerilog synthesis compilers……Page 59
1.6.2.1 Single-file and multi-file compilation……Page 60
1.6.3 Constraints……Page 61
1.7 SystemVerilog lint checkers……Page 62
1.8 Logic Equivalence Checkers……Page 63
1.9 Summary……Page 64
2.1 Modules and procedural blocks……Page 65
One-line comments……Page 66
Block comments……Page 67
Pragmas……Page 68
2.2.2 White space……Page 69
2.2.3 Reserved keywords……Page 70
2.2.4 Keyword backward compatibility — ‘beginkey words……Page 72
2.2.5 Identifiers (user-defined names)……Page 75
2.2.6 Naming conventions and guidelines……Page 76
2.2.7 System tasks and functions……Page 77
2.3 Modules……Page 78
2.4 Modules instances and hierarchy……Page 80
2.4.1 Port order connections……Page 81
2.4.2 Named port connections……Page 82
2.4.3 The dot-name inferred named port connection shortcut……Page 83
2.4.4 The dot-star inferred named port connection shortcut……Page 84
2.5 Summary……Page 85
3.1 Four-state data values……Page 86
3.2.1 Literal integer values……Page 87
3.2.1.1 Mismatched size and value rules……Page 89
3.2.2 Vector fill literal values……Page 90
3.3 Types and data types……Page 91
3.4 Variable types……Page 92
3.4.1 Synthesizable variable data types……Page 93
3.4.2 Variable declaration rules……Page 95
3.4.3 Variable assignment rules……Page 99
3.4.5 In-line variable initialization……Page 100
3.5 Net types……Page 101
3.5.1 Synthesizable net types……Page 102
3.5.2 Net declaration rules……Page 104
3.5.3 Implicit net declarations……Page 105
3.5.4 Net assignment and connection rules……Page 108
3.6.1 Synthesizable port declarations……Page 109
3.6.2 Non synthesizable port declarations……Page 112
3.6.3 Module port declaration recommendations……Page 113
3.7 Unpacked arrays of nets and variables……Page 114
3.7.1 Accessing array elements……Page 115
3.7.3 Array list assignments……Page 116
3.7.4 Bit-select and part-select of array elements……Page 117
3.8 Parameter constants……Page 118
3.8.1 Parameter declarations……Page 119
3.8.2 Parameter overrides (parameter redefinition)……Page 122
3.10 Summary……Page 124
4.1 User-defined types……Page 126
4.2 SystemVerilog packages……Page 127
4.2.1 Package declarations……Page 128
4.2.2.1 Wildcard import of package items……Page 129
4.2.2.2 Explicit importing specific package items……Page 130
4.2.2.3 Placement of package import statements……Page 131
4.2.2.4 Direct package references using the scope resolution operator……Page 132
4.2.3 Importing from multiple packages……Page 133
4.2.4 Package chaining……Page 134
4.2.5 Package compilation order……Page 135
4.2.6 Synthesis considerations……Page 136
4.3 The $unit declaration space……Page 137
4.4.1.1 Implicit-style enumerated declarations……Page 139
4.4.1.2 Explicit-style enumerated declarations……Page 140
4.4.1.5 Enumerated type label scope……Page 141
4.4.2 Importing enumerated types from packages……Page 142
4.4.3 Enumerated type assignment rules……Page 143
4.4.4 Enumerated type method……Page 146
4.5.1 Structure declarations……Page 149
4.5.3 Assigning to entire structures……Page 150
4.5.4 Typed and anonymous structures……Page 151
4.5.6 Packed and unpacked structures……Page 152
4.5.7 Passing structures through ports and to tasks and functions……Page 154
4.5.9 Synthesis considerations……Page 155
4.6.1 Typed and anonymous unions……Page 156
4.6.3 Unpacked, packed and tagged unions……Page 157
4.6.4 Passing unions through ports and to tasks and functions……Page 159
4.7 Using arrays with structures and unions……Page 161
4.8 Summary……Page 164
Chapter 5 RTL Expression Operators……Page 165
5.1.2 X-optimism and X-pessimism……Page 166
5.1.3 Expression vector sizes and automatic vector extension……Page 168
5.1.5 Integer (vector) and real (floating-point) expressions……Page 169
5.2 Concatenate and replicate operators……Page 170
5.3 Conditional (ternary) operator……Page 174
5.4 Bitwise operators……Page 177
5.5 Reduction operators……Page 182
5.6 Logical operators……Page 184
5.6.1 Difference between negate and invert operations……Page 185
5.6.2 Short circuiting logical operations……Page 187
5.7 Comparison operators (equality and relational)……Page 188
5.8 Case equality (identity) operators……Page 192
5.9 Set membership (inside) operator……Page 195
5.10 Shift operators……Page 197
5.10.1 Synthesizing shift operations……Page 198
5.10.2 Synthesizing rotate operations……Page 201
5.11 Streaming operators (pack and unpack)……Page 205
5.12 Arithmetic operators……Page 208
5.12.1 Integer and floating-point arithmetic……Page 210
5.12.2 Unsigned and signed arithmetic might synthesize to the same gates……Page 212
5.13 Increment and decrement operators……Page 213
5.13.1 Proper usage of increment and decrement operators……Page 214
5.13.2 An example o f correct usage o f increm ent and decrem ent operators……Page 216
5.13.3 Compound operations with increment and decrement operators……Page 218
5.13.4 An anecdotal story on the increment and decrement operators……Page 219
5.14 Assignment operators……Page 220
5.15 Cast operators and type conversions……Page 222
5.15.1 Type casting……Page 224
5.15.2 Size casting……Page 226
5.15.3 Signedness casting……Page 230
5.16 Operator precedence……Page 233
5.17 Summary……Page 234
6.1 System Verilog procedural blocks……Page 235
6.1.1 Sensitivity lists……Page 236
6.1.2 Begin-end statement groups……Page 239
6.2 Decision statements……Page 240
6.2.1 if-else statements……Page 241
6.2.2 Case statements……Page 247
6.2.2.1 Case versus case…inside……Page 248
6.2.2.3 Case item priority and automatic synthesis optimization……Page 249
6.3 Looping statements……Page 252
6.3.1 For loops……Page 253
6.3.1.1 Static loops versus data-dependent loops……Page 254
6.3.1.2 Zero-delay and timed loops……Page 255
6.3.2 Repeat loops……Page 257
6.3.3 While and do-while loops……Page 259
6.3.4 For each loops and looping through arrays……Page 260
6.4.1 The continue and break ju m p statements……Page 263
6.4.2 The disable ju m p statement……Page 264
6.5 No-op statement……Page 266
6.6.1 Functions……Page 267
Function returns……Page 268
Function arguments……Page 269
Function input default values……Page 270
Parameterized functions……Page 271
6.6.2 Tasks……Page 272
6.7 Summary……Page 273
Chapter 7 Modeling Combinational Logic……Page 274
7.1 Continuous assignments (Boolean expressions)……Page 275
7.1.2 Multiple continuous assignments……Page 277
7.1.3 Using both continuous assignments and always procedures……Page 278
7.2 The always and alw ayscom b procedures……Page 279
7.2.2 Modeling with the general purpose always procedure……Page 280
Incomplete sensitivity lists — a modeling gotcha……Page 281
The obsolete always @* procedure……Page 282
7.2.3 Modeling with the RTL-specific always combprocedure……Page 283
7.2.4 Using blocking (combinational logic) assignments……Page 284
7.2.5 Avoiding unintentional latches in combinational logic procedures……Page 285
7.3 Using functions to represent combinational logic……Page 286
7.4 Combinational logic decision priority……Page 288
7.4.2 The unique and uniqueO decision modifiers……Page 289
7.4.3 The obsolete parallelcase synthesis pragma……Page 293
7.5 Summary……Page 294
Chapter 8 Modeling Sequential Logic……Page 296
8.1.1 Synthesis requirements for RTL sequential logic……Page 297
8.1.2 Always procedures and alwaysj ff procedures……Page 298
8.1.3 Sequential logic clock-to-Q propagation and setup/hold times……Page 299
Sequential logic clock-to-Q propagation delays……Page 300
8.1.4 Using nonblocking (sequential logic) assignments……Page 301
8.1.4.1 Execution order of events within an event region……Page 303
8.1.4.2 Improper use of blocking assignments in sequential flip-flop behavior……Page 305
8.1.4.3 Using blocking assignments for temporary variables……Page 306
8.1.5 Synchronous and asynchronous resets……Page 309
8.1.5.2 Synchronous reset RTL flip-flop models……Page 310
8.1.5.3 Asynchronous reset RTL flip-flop models……Page 311
8.1.5.4 Chip-enable flip-flops……Page 313
8.1.5.5 Asynchronous set-reset flip-flops……Page 314
8.1.5.7 Flip-flop power-up values (FPGA-specific……Page 317
8.1.6 Multiple clocks and clock domain crossing (CDC)……Page 318
8.1.7.1 Adding unit delays to sequential logic RTL models……Page 320
8.1.7.2 Inferred combinational logic in a sequential logic procedure……Page 321
8.2 Modeling Finite State Machines (FSMs)……Page 322
8.2.1 M ealy and M oore F SM architectures……Page 324
8.2.2 State encoding……Page 325
8.2.3.1 Three process state machine models……Page 328
8.2.3.2 Two process state machine models……Page 330
8.2.3.3 One process state machine models……Page 331
8.2.4 A complete FSM example……Page 332
8.2.5 Reverse case statement one-hot decoder……Page 336
8.3 M odeling memory devices such as RAMs……Page 340
8.3.1 Modeling asynchronous and synchronous memory devices……Page 342
8.3.2 Loading memory models using $ read me mb and Sreadmemh……Page 343
8.4 Summary……Page 345
9.1 Modeling Latches……Page 346
9.1.1 Modeling latches with the general purpose always procedure……Page 347
9.1.2 Modeling latches with the always latch procedure……Page 348
9.2 Unintentional latch inference……Page 350
9.3 Avoiding latches in intentionally incomplete decisions……Page 352
9.3.1 Latch avoidance coding style trade-offs……Page 353
9.3.2 A small example to illustrate avoiding unintentional latches……Page 355
9.3.3 Latch avoidance style 1 — D efault case item with known values……Page 358
9.3.4 Latch avoidance style 2— Pre-case assignment, known values……Page 361
9.3.5 Latch avoidance style 3 — unique and priority decision modifiers……Page 363
9.3.5.2 The uniqueO decision modifier……Page 364
9.3.5.4 Decision modifier example……Page 366
9.3.6 Latch avoidance style 4 — X assignments for unused decision values……Page 368
9.3.7 Latch avoidance style 5 — the full case synthesis pragma……Page 373
9.3.8 Additional notes about synthesis pragm as……Page 374
9.4 Summary……Page 376
Chapter 10 Modeling Communication Buses — Interface Ports……Page 377
10.1 Interface port concepts……Page 378
10.1.1 Traditional Verilog bus connections……Page 379
10.1.2 SystemVerilog interface definitions……Page 383
10.1.4 Differences between modules and interfaces……Page 387
10.2.1 Generic interface ports……Page 388
10.3 Interface modports……Page 389
10.3.1 Specifying which m odport view to use……Page 390
10.3.2 Using modports to define different sets of connections……Page 393
10.4 Interface methods (tasks and functions)……Page 394
10.4.1 Calling methods defined in an interface……Page 396
10.4.3 Abstract, non-synthesizable interface methods……Page 397
10.5 Interface procedural code……Page 398
10.6 Parameterized interfaces……Page 400
10.7 Synthesizing interfaces……Page 401
10.8 Summary……Page 404
Chapter 3: Net and Variable types……Page 405
Chapter 5: RTL Expression Operators……Page 406
Chapter 6: RTL Programming Statements……Page 407
Chapter 8: Modeling Sequential Logic……Page 408
Chapter 9: Modeling Latches and Avoiding Unintentional Latches……Page 409
Chapter 10: Modeling Communication Buses — Interface Ports……Page 410
B.1 All SystemVerilog-2012 reserved keywords……Page 411
B.2 Verilog-1995 reserved keywords……Page 413
B.4 Verilog-2005 reserved keywords……Page 414
B.5 SystemVerilog-2005 reserved keywords……Page 415
B.8 SystemVeriIog-2017 reserved keywords……Page 416
Appendix C X Optimism and X Pessimism in RTL Models……Page 417
C.1 Introducing My X……Page 418
C.2.1 Uninitialized 4-state variables……Page 419
C.2.2 Uninitialized registers and latches……Page 420
C.2.7 Out-of-range bit-selects and array indices……Page 421
C.2.10 User-assigned X values in hardware models……Page 422
C.3 An optimistic X — is that good or bad?……Page 423
C.3.1 If…else statements……Page 424
C.3.2 Case statements without a default-X assignment……Page 427
C.3.3 Casex, casez and case…inside statements……Page 428
C.3.4 Bitwise, unary reduction, and logical operators……Page 431
C.3.7 Array index with X or Z bits for write operations……Page 432
C.3.8 Net data types……Page 433
C.3.9 Posedge and negedge edge sensitivity……Page 434
C.4 A pessimistic X — is that any better?……Page 435
C.4.1 If…else statements with X assignments……Page 436
C.4.2 Conditional operator……Page 437
C.4.3 Case statements with X assignments……Page 439
C.4.5 Bitwise, unary reduction, and logical operators……Page 440
C.4.6 Equality, relational, and arithmetic operators……Page 441
C.4.7 User-defined primitives……Page 442
C. 4.9 Shift operations……Page 443
C.5 Eliminating my X by using 2-state simulation……Page 444
C.6 Eliminating some of my X with 2-state data types……Page 446
C.7 Breaking the rules— simulator-specific X-propagation options……Page 448
C.8 Changing the rules — A SystemVerilog enhancement wish list……Page 449
C.9 Detecting and stopping my X at the door……Page 450
C.10.1 2-state versus 4-state guidelines……Page 452
C.10.4 Trapping X guidelines……Page 453
C.11 Conclusions……Page 454
C.12 Acknowledgments……Page 455
C.13 References……Page 456
Books……Page 457
Conference papers……Page 458
Index……Page 460

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